#ifndef __VICREG_H_
#define __VICREG_H_

#include "../PUBLIC/public.h"
//向量中断控制器相关寄存器

#define PERIPHBASE              0xF0000000      // "MRC p15, 4, %0, c15, c0, 0\n"
#define GICC_ADDR               (PERIPHBASE + 0x0100)
#define GICD_ADDR               (PERIPHBASE + 0x1000)

#define GICC_CTLR			    __REG(GICC_ADDR + 0x00)
#define GICC_IAR                __REG(GICC_ADDR + 0x0C)
#define GICC_EOIR               __REG(GICC_ADDR + 0x10)

#define GICD_CTLR               __REG(GICD_ADDR + 0x00)
#define GICD_TYPER              __REG(GICD_ADDR + 0x04)
#define GICD_IIDR               __REG(GICD_ADDR + 0x08)
#define GICD_IGROUPR0           __REG(GICD_ADDR + 0x0080)
#define GICD_IGROUPR1           __REG(GICD_ADDR + 0x0084)
#define GICD_IGROUPR2           __REG(GICD_ADDR + 0x0088)
#define GICD_ISENABLER0         __REG(GICD_ADDR + 0x0100)
#define GICD_ISENABLER1         __REG(GICD_ADDR + 0x0104)
#define GICD_ISENABLER2         __REG(GICD_ADDR + 0x0108)
#define GICD_ITARGETSR0         __REG(GICD_ADDR + 0x0800)   // 每32bit配置4个中断
#define GICD_ITARGETSR13        __REG(GICD_ADDR + 0x0834)
#define GICD_ITARGETSR21        __REG(GICD_ADDR + 0x0854)   // ID(32 + 54) offset 2

#define BASE_ADDR_CH0           0xC0002000  // 0 to 31 IRQ
#define BASE_ADDR_CH1           0xC0003000  // 32 to 63 IRQ

#define VICIRQSTATUS_CH0        __REG(BASE_ADDR_CH0 + 0x00)
#define VICIRQSTATUS_CH1        __REG(BASE_ADDR_CH1 + 0x00)
#define VICRAWINTR_CH1          __REG(BASE_ADDR_CH1 + 0x08)
#define VICINTSELECT_CH0        __REG(BASE_ADDR_CH0 + 0x0C)
#define VICINTSELECT_CH1        __REG(BASE_ADDR_CH1 + 0x0C)
#define VICINTENABLE_CH0        __REG(BASE_ADDR_CH0 + 0x10)
#define VICINTENABLE_CH1        __REG(BASE_ADDR_CH1 + 0x10)
#define VICINTENCLEAR_CH0       __REG(BASE_ADDR_CH0 + 0x14)
#define VICINTENCLEAR_CH1       __REG(BASE_ADDR_CH1 + 0x14)
#define VICSOFTINT_CH0          __REG(BASE_ADDR_CH0 + 0x18)
#define VICSOFTINT_CH1          __REG(BASE_ADDR_CH1 + 0x18)
#define VICSOFTINTCLEAR_CH1     __REG(BASE_ADDR_CH1 + 0x1C)
#define VICSWPRIORITYMASK_CH1   __REG(BASE_ADDR_CH1 + 0x24)
#define VICVECTADDR_UART0       __REG(BASE_ADDR_CH0 + 0x011C)
#define VICVECTADDR_GPIOB       __REG(BASE_ADDR_CH1 + 0x0158)
#define VICVECTADDR_TIMER0      __REG(BASE_ADDR_CH0 + 0x015C)
#define VICVECTADDR_TIMER2      __REG(BASE_ADDR_CH0 + 0x0164)
#define VICVECTPRIORITY_GPIOB   __REG(BASE_ADDR_CH1 + 0x0258)
#define VICADDRESS_CH0          __REG(BASE_ADDR_CH0 + 0x0F00)
#define VICADDRESS_CH1          __REG(BASE_ADDR_CH1 + 0x0F00)



void vic_init(int num, u32 isr);

#endif

